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total latency for the 4-stage pipeline is 320 ns (80 ns x 4) and the total latency for the 11-stage pipeline is 330 ns (30 ns x 11) The difference between the new total latency and the original total latency of 280 ns represents the internal fragmentation Hence, the internal fragmentation for the 4-stage design is 40 ns (320 ns - 280 ns), and the internal fragmentation for the 11-stage design is 50 ns (330 ns - 280 ns) It can be concluded that the 4-stage design is more efficient than the 11-stage design in terms of incurring less overhead due to internal fragmentation Of course, the 11-stage design yields a throughput that is 93 (280 n s / 3 0 ns) times that of a nonpipelined design, while the 4-stage design's throughput is only 35 (280 n s / 80 ns) times that of a nonpipelined design As can be seen in both designs, the internal fragmentation has hindered the attainment of the idealized throughput increase by factors of 11 and 4 for the 11-stage and the 4-stage pipelines, respectively 221 J2 Hardware Requirements In most realistic engineering designs, the goal is not simply to achieve the best possible performance, but to achieve the best performance/cost ratio Hence, in addition to simply maximizing the throughput (performance) of an instruction pipeline, hardware requirements (cost) must be considered In general, higher degrees of pipelining will incur greater costs in terms of hardware requirements Clearly there is the added cost due to the additional buffering between pipeline stages We have already seen in the model presented in Section 2113 that there is a point beyond which further pipelining yields diminishing returns due to the overhead of buffering between pipeline stages Besides this buffering overhead, there are other, and more significant, hardware requirements for highly pipelined designs In assessing the hardware requirements for an instruction pipeline, the first thing to keep in mind is that for a it-stage instruction pipeline, in the worst case, or actually best case in terms of performance, there are k instructions concurrently present in the pipeline There will be an instruction resident in each pipeline stage, with a total of it instructions all in different phases of the instruction cycle Hence, the entire pipeline must have enough hardware to support the concurrent processing of k instructions in the k pipeline stages The hardware requirements fall into three categories: (1) the logic required for control and data manipulation in each stage, (2) register-file ports to support concurrent register accessing by multiple stages, and (3) memory ports to support concurrent memory accessing by multiple stages We first examine the four-stage instruction pipeline of Figure 28(a) Assuming a load/store architecture, a typical register-register instruction will need to read the two register operands in the first stage and store the result back to a register in the fourth stage A load instruction will need to read from memory in the second stage, while a store instruction will need to write to memory in the fourth stage Combining the requirements for all four stages, a register file with two read ports and one write port will be required, and a data memory interface capable of performing one memory read and one memory write in every machine cycle will be required In addition, the first stage needs to read from the instruction memory in every cycle for instruction fetch If a unified (instruction and data) memory is used, then this memory must be able to support two read accesses and one write access in every machine cycle.

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Once the prompt is printed, we ll call fgets() to read in a line of text from the console. We ll store the line in the char array title[ dvdNum ]. We ll tell fgets() to limit input to the length of that char array, which is kMaxTitleLength. The last parameter, stdin, tells fgets() to read its input from the console, as opposed to reading from a file.

fgets( title[ dvdNum ], kMaxTitleLength, stdin ); }

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Take a look at the first parameter we passed to fgets():

title[ dvdNum ]

.