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So far, each of the examples presented in this chapter have treated files as a sequential stream of bytes. When dvdFiler read from a file, it started from the beginning of the file and read the contents, one byte at a time or in larger chunks, but from the beginning straight through until the end. This sequential approach works fine if you intend to read or write the entire file all at once. As you might have guessed, there is another model. Instead of starting at the beginning and streaming through a file, you can use a technique called random file access. The Standard Library provides a set of functions that let you reposition the file position indicator to any location within the file, so that the next read or write you do occurs exactly where you want it to. Imagine a file filled with 100 longs, each of which was 4 bytes long. The file would be 400 bytes long. Now, suppose you wanted to retrieve the tenth long in the file. Using the sequential model, you would have to do ten reads to get the tenth long into memory. Unless you read the entire file into memory, you ll constantly be reading a series of longs to get to the long you want. Using the random access model, you would first calculate where in the file the tenth long starts. Then, you d jump to that position in the file and read just that long. To move the file position indicator just before the tenth long, you d skip over the first nine longs (9 * 4 = 36 bytes).

There are a number of useful functions you ll need to know about in order to randomly access your files. fseek() moves the file position indicator to an offset you specify, relative to either the beginning of the file, the current file position, or the end of the file:

int fseek( FILE *fp, long offset, int whence );

Step 3 Press ENTER on the keyboard to continue booting Once the system is up and running, go online and nd out whether a more recent version of your BIOS is available Your rst stop should be your PC maker s Web site If it does not have this information available, try your motherboard manufacturer or the BIOS maker

the reads and writes, then effectively total sequential execution is carried out and no hazard can occur If the stage performing the read is positioned later in the pipeline than the stage performing the write, then RAW hazards can never occur; the reason is that all the writes of leading instructions will be completed before the trailing instructions perform their reads Since pipeline hazards are caused by potential violations of program dependences, a systematic procedure for identifying all the pipeline hazards that can occur in an instruction pipeline can be formulated by considering each dependence type in turn The specific procedure employed in this chapter examines program dependences in the following order 1 Memory data dependence a Output dependence b Anti-dependence c True data dependence 2 Register data dependence a Output dependence b Anti-dependence c True data dependence 3 Control dependence We illustrate this procedure by applying it to the six-stage TYP instruction pipeline First, memory data dependences are considered A memory data dependence involves a common variable stored in memory that is accessed (either read or write) by two instructions Given a load/store architecture, memory data dependences can only occur between load/store instructions To determine whether pipeline hazards can occur due to memory data dependences, the processing of load/store instructions by the pipeline must be examined Assuming a split cache design, in the TYP pipeline, only the M E M stage can access the D-cache Hence, all accessing of memory locations by load/store instructions must and can only occur in the MEM stage; there is only one stage in the pipeline that performs reads and writes to the data memory Based on the necessary conditions presented in Figure 215 no pipeline hazards due to memory data dependences can occur in the TYP pipeline Essentially, all accesses to the data memory are performed sequentially, and the processing of all load/store instructions is done in the total sequential execution mode Therefore, for the TYP pipeline, there are no pipeline hazards due to memory data dependences Register data dependences are considered next To determine pipeline hazards that can occur due to register data dependences, all pipeline stages that can access the register file must be identified In the T Y P pipeline, all register reads occur in the RD stage and all register writes occur in the WB stage An output (WAW) dependence, denoted ib j, indicates that an instruction i and a subsequent instruction j both share the same destination register To enforce the output dependence, instruction i must write to that register first; then instruction j can write to that same register In the TYP pipeline, only the WB stage can perform writes to the.

You ll pass your FILE pointer as the first parameter, a long offset as the second parameter, and SEEK_SET, SEEK_CUR, or SEEK_END as the third parameter. SEEK_SET represents the beginning of the file. SEEK_CUR represents the current position, and SEEK_END represents the end of the file (in which case you ll probably use a negative offset).

file position indicator:

Do not ash your system BIOS at this time!